to simplify processor design by eliminating hardware
that only single execution cycle instructions can access the
can schedule them to avoid conflicts. This also means that
LOAD/STORE and branch instructions have a one-cycle delay to
account for. However, because of the importance of multiply
and divide instructions, a special HI/LO pair of
multiply/divide registers exist which do have hardware
interlocks, since these take several cycles to execute and
The project eventually lead to the commercial
MIPS R2000processor.
(1995-02-09)